With the advances in semiconductor technology, integrated circuits (IC) having multi-functional circuit modules composed of a large number of transistors and/or other semiconductor devices integrated on a silicon die are more and more popular. For example, in integrated circuits of VLSI and ULSI, the number of transistors and/or other semiconductor devices included is huge and the devices are densely packed together. Therefore, it is important to have isolation structures between adjacent transistors/devices to prevent short circuit occurring between neighboring transistors/devices. The most commonly used isolation structures may include field oxide isolation, and trench isolation such as shallow trench isolation (“STI”). However, as line width of semiconductor device falls to below 0.25 μm, isolating devices using a field oxide layer become infeasible and trench isolation becomes the only means of device isolation.
Furthermore, in an integrated circuit, different circuit modules and/or transistors and other devices in the same chip may operate in different voltage regimes. For example, in an integrated switching-mode power supply, which may generally comprise a power transistor and a control circuit for switching the power transistor ON and OFF to convert a supply voltage into a desired output voltage, the power transistor may have an operating voltage much higher than an operating voltage of transistors constituting the control circuit. In order to have area-efficient high voltage device with low voltage control devices fabricated on a same die in a technology, dual gate insulation layers are desired. For example, a first gate insulation layer of a first thickness (e.g. 100 {acute over (Å)}) is desired for forming both high voltage devices and low voltage devices, e.g. functioning as a gate insulation layer for gates of high voltage devices and low voltage devices; a second gate insulation layer of a second thickness (e.g. 500 {acute over (Å)}), which is relatively thicker than the first thickness, is desired for forming high voltage devices, e.g. functioning as a gate insulation layer of a field plate atop a drift region (in most cases, the field plate may comprise a portion of the gate extended on top of the drift region) of high voltage devices. Therefore, dual gate insulation layers are necessary to form devices having different voltage ratings on a die. A relatively thin gate insulation layer supports the formation of both high voltage rated devices and low voltage rated fast devices while a relatively thick gate insulation layer supports the formation of high voltage rated devices.
From the above, it can be understood that manufacturing semiconductor devices having dual gate insulation layers with trench isolation tends to be necessary for fabricating an integrated circuit based on a reduction of fabrication line width. Nevertheless, several drawbacks may become noticeable when forming dual gate insulation layers of a semiconductor device having trench isolation (e.g. Shallow trench Isolation a.k.a. STI) structures with conventional manufacturing processes. For example, FIGS. 1A through 1C are cross-sectional views for illustrating a conventional process for fabricating semiconductor devices having dual gate insulation layers and STI structures. In the conventional manufacturing process, a thick gate oxide layer 12 is usually formed with thermal oxidation after the formation of a STI structure 11 in a substrate 10, as illustrated in FIG. 1A. The STI structure 11 may define a first active region HV of high-voltage regime and a second active region LV of low-voltage regime, and may also be used for isolating devices that will be formed on each of the first and second active regions. The thick gate oxide layer 12 is provided for forming semiconductor devices operating at the high-voltage regime, for example. Since the thick gate oxide layer 12 is typically formed by thermal oxidation, growing of the thick gate oxide layer 12 may consume a relatively large portion of the underlying semiconductor substrate 10, and thus the thick gate oxide layer 12 may have a substantial portion infringed down into the substrate 10, as illustrated in FIG. 1A. If a thickness of the thick gate oxide layer 12 exceeds 150 {acute over (Å)}, it may cause silicon stress near the edges of the STI structures 11 due to incommensurate growth of the thick gate oxide layer 12, leading to silicon defects, which may be a leakage source. In addition, due to an oxidation rate difference over the semiconductor substrate 10 (such as silicon substrate) and the STI structures 11 (such as oxide STI structures), the thick gate oxide layer 12 formed by thermal oxidation over the STI regions 11 would be much thinner than that formed on the semiconductor substrate 10, which may be a main source of pits that would appear near the edges of the STI structures 11 in the following manufacturing steps. In a subsequent step, as illustrated in FIG. 1B, the thick gate oxide layer 12 over a portion of the substrate whereon a thin gate oxide layer should be formed is removed and the portion of the substrate 10 is exposed. During the removing process of the thick gate oxide layer 12 and subsequent cleaning processes, edges of the STI structures 11 may be over etched and pits 13 may appear, which may result in a leaky N+/P-well or P+/N-well junction near the edges of the STI structures 11 during subsequent active region (such as source/drain region) formation processes. In the following, as illustrated in FIG. 1C, a thin gate oxide layer 14 is formed by thermal oxidation over the exposed portion of the substrate 10, and then gates 15, source/drain regions 16 etc. are formed. The semiconductor devices formed on the first active region HV illustrated in FIG. 1C may comprise lateral DMOS (double diffused metal-oxide semiconductor) transistors, and the semiconductor devices formed on the second active region illustrated in FIG. 1C may comprise low-voltage MOS (metal-oxide semiconductor) transistors. According to the conventional fabrication method, a leaky N+/P-well or P+/N-well junction may appear near the edges of the STI structures 11 due to existence of pits 13.
According to the conventional manufacturing process, junction leakage and threshold variation problems may be aggravated as the silicon stress and size of the pits 13 near the edges of the STI structures 11 increase, especially with the reduction of line width of semiconductor devices for reducing die size and achieving high integration. Therefore, it is tough to incorporate a dual gate insulation structure and a trench isolation structure (such as STI structure) with the conventional fabrication process. The device yield may be quite low.